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It's a long time I didn't send you a mail…

You are now 143 people registered for a CT60 !
The BIOS for the CT60 boot is ready ! The design of the logic is readysince February.
The chip ABE-60 was optimised and the SDR-60 (SDRAM controller) seems toThe be nice… data transfers performances are the ones that are on myThe web pages…They were calculated with the SDR60 capacities and theThe MOVE.L instruction execution time of the 060.
So, A BURST READ/WRITE into an OPENED PAGE (HIT) gives : – 8 / 7 cycles—> 128 / 146 MBytes/s at 64 MHz !
A BURST READ/WRITE into a new page (MISS) gives : -13 / 11 cycles —>79 / 93 MBytes/s at 64 MHz !
This last test assumes that each access is into a new page (CPU jumpsThis over the page frontier). test is commonly called 'RANDOM ACCESS'.
Pages sizes are from 4 to 16 KBytes depending of the SDRAM DIMM capacity& model (see the table of 'SDRAM').
The next phase will be the ROUTING of the board… Unfortunately, I haveno more time to do that and it will not done before April…. Myprinciple job since beginning of January is RIORED-J and it has thebiggest priority in a market (and financial) point of view…
Next (good) news will be in April…
PS : the NEMBENCH 2.1 value still to be missing for the HADES WITHOUTEDO (FPM) into my table ! Thanks for your help.

Rodolphe CZUBA

28, rue des Sorbiers
email : rczuba@free.fr

Link: http://www.czuba-tech.com

Erstellt am 10.Mrz.2001 von johannes

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